Reliable, High-Speed & Accurate Trading Partner
A Cyberport Incubation Program supported Company
Hardware Acceleration Risk Enforcement for HKEX OCG-C Pre-trade
To meet ultra-low-latency demands of pre-trade risk management in high-frequency trading, our CRC-32C verification module targets the HKEX OCG-C binary protocol. Implemented in Verilog on Xilinx Virtex UltraScale+ FPGA within an Arista 7130 Layer-1+ switch, it supports comprehensive CRC recalculation and fast differential updates for modified order messages. Post-synthesis validates 250 MHz operation with <5μs latency and minimal resources, ensuring deterministic packet integrity for sector derivatives trading.
Empower Your Trading with FPGA Risk Acceleration
Our hardware-accelerated pre-trade solution leverages Xilinx Virtex UltraScale+ FPGA for line-rate CRC-32C validation and enforcement of rules like capital limits, position concentration, and self-trading prevention. Co-located in the data path, it eliminates CPU jitter for deterministic performance, achieving sub-microsecond latencies and boosting market stability in high-throughput sector derivatives.
Ultra-Low Latency Risk Acceleration for HKEX Trading
In high-stakes HFT, our inline solution delivers unbreakable pre-trade enforcement via HKEX OCG-C protocol. Crafted in Verilog for Xilinx Virtex UltraScale+ FPGAs integrated into Arista 7130 Layer-1+ switches, it combines full CRC-32C recalculation with optimized differential updates. Clocking at 250 MHz with <5ns per cycle, it outpaces software (e.g., Python/C++) using pure logic gates for checksum validation. Simulations confirm bit-accurate correctness for New/Amend Order messages, empowering traders to navigate volatile markets with liquidity and regulatory compliance at finance speeds.
FPGA-based OCG Risk Checker
Our deeply pipelined design processes HKEX OCG-C messages entirely in FPGA fabric via low-latency AXI and Layer-1+ matrix. Client-Side I/O Controller parses TCP/IP for line-rate extraction; CRC Verification Module handles checksum/integrity; messages classify (e.g., New/Amend Orders) and throttle bursts. Multi-stage Risk Engine enforces capital/position/self-trade rules using on-chip Order Record Register for stateful context. Approved orders route to Server-Side I/O for HKEX transmission; dedicated handler syncs responses. This end-to-end pipeline delivers real-time validation at 10 Gbps, with sub-5µs latency.
Orion Trading Platform
The OCG Risk Checker integrates into HKEX's Orion Trading Platform (OTP-C) as an inline enforcer between broker-supplied systems (BSS) and OCG-C Gateway. It preserves network/protocol integrity (CRC-32C mandatory) for pre-trade checks without altering exchange pipelines. Deployed on Arista 7130, it supports New/Amend/Cancel Orders per OCG-C binary spec.
Accelerated Throttle & Risk Enforcement
We use FPGAs for fast risk categorization, sorting orders efficiently and swiftly adjusting exposures to enhance diversity and protect against market volatility.
Our approach accelerates deployment of custom risk strategies, maximizing computational efficiency and allowing execution of algorithms quickly in the Arista switch fabric.
At FinSiliconX, we harness hardware acceleration for HFT efficiency and risk minimization. Advanced CRC-32C paths ensure cycle-accurate verification, with findings showing baseline recalculation optimal for scattered real-world mutations.
FPGA Acceleration is the Key
